FTA is fault tree analysis, used for identifying causes required for a particular fault/event to take place.
This technique uses basic symbols of electronic & logic field. The Fundamental symbol used are AND & OR gate.
Truth table for AND & OR gates:
Symbols of AND & OR gates:
The failure mode being studied is called head event.
The basic concept of this technique is to put all effecting events in a logical form. Take a case of motor stoppage. The motor can be stopped due to following reasons:
- Power loss
- Coil Damage
- Process interlock operated
Further power loss can occur if the incomer power supply fails & the emergency generator also fails at the same time. Over load can occur due to chocking in pipe line, or, the isolation valve is closed. Coil can damage due to over current or moisture ingress. Process interlock can be operated due to instrument malfunction or real high vibration.
The Logic tree can be built as follows:
All the identified events can be given probability of failure depending upon MTBF calculated from past events. In case both events are required for resultant event to occur ie. AND gate, the probabilities are multiplied. In case, any one input can have the resultant impact ie. OR gate probabilities are added.
The FTA Analysis is done for finding out all probable faults possible. This enables us to attack on right cause for identify & eliminating the fault.